AMD and Intel have teamed up to create a shared AI computing standard that could make future PCs and laptops faster at running AI applications while giving software developers a single platform that works across both companies’ processors.
The new technology is designed to improve how CPUs handle AI workloads, leading to more efficient AI processing and broader software compatibility when compatible hardware arrives.
The two companies have published the full specification for AI Compute Extensions (ACE), establishing a shared x86 standard for processing AI matrix workloads on future processors.
The specification has reached version 1.15, giving developers a stable target for AI and high-performance computing software before compatible hardware becomes available.
Neither company has announced an ACE-capable processor. Compatible chips are not expected until around 2028, meaning the software standard has arrived well before the hardware designed to support it.
AI workloads rely heavily on matrix multiplication, but traditional x86 SIMD extensions were designed mainly for vector processing.
AVX and its later versions process long, one-dimensional sets of values. AI models, however, frequently work with two-dimensional matrices, making conventional vector instructions less efficient for these calculations.
GPUs addressed this problem with dedicated tensor hardware. CPUs could still process AI workloads, but they lacked a common x86 instruction set designed specifically for matrix operations.
ACE adds eight two-dimensional tile registers to the x86 architecture.
Each tile register can hold a 16-by-16 matrix of 32-bit values, allowing processors to handle matrix data in a form that better matches AI workloads.
The new instructions use an outer-product approach, completing more matrix calculations with each instruction than a comparable AVX10 operation.
AMD and Intel say ACE can provide up to 16 times the matrix-compute density of an equivalent AVX10 multiply-accumulate operation while using the same number of input vectors.
This does not mean every AI workload will run 16 times faster. Actual performance will depend on factors such as memory bandwidth, compiler support, and the amount of chip space manufacturers dedicate to ACE hardware.
However, ACE should reduce instruction overhead because processors will need fewer instructions to complete the same amount of matrix work. It could also limit the unnecessary movement of data between registers.
ACE supports data formats commonly used for artificial intelligence, including INT8, FP8, and BF16.
It also supports block-scaled formats developed through the Open Compute Project. These lower-precision formats can reduce memory use and increase processing efficiency for AI models.
This gives ACE a more AI-focused set of capabilities than AVX10 alone.
Intel already offers Advanced Matrix Extensions (AMX) in its Xeon server processors.
However, AMD and Intel have not adopted Intel’s existing AMX instructions as the common x86 standard. Instead, they developed ACE as a separate shared extension that uses parts of the existing AMX framework.
Eight of the 11 authors named in the ACE whitepaper are AMD engineers, while three are from Intel.
ACE is intended for a wider range of x86 products than Intel’s server-focused AMX implementation. Manufacturers could add it to servers, laptops, and embedded devices, depending on their individual hardware designs.
ACE will not make x86 processors direct competitors to Nvidia GPUs for large AI training jobs or the most demanding inference workloads.
Instead, it is designed to provide a common matrix-compute foundation for AI tasks that already run on CPUs but currently operate less efficiently.
Consistent implementation by AMD and Intel could give software developers one shared x86 path for matrix processing across different processors.
ACE does not turn CPUs into GPUs, but it gives future x86 processors dedicated instructions for AI calculations that traditional vector extensions were not designed to handle.
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